1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more specifically, to an improvement of a sense amplifier of a flash memory.
2. Description of the Background Art
In a flash memory, the threshold voltage of a memory cell is made low or high by the program operation or an erase operation so as to distinguish between data xe2x80x9c0xe2x80x9d and data xe2x80x9c1.xe2x80x9d In a DINOR (DIvided NOR) type flash memory under development, the state of low threshold voltage is defined as a programmed state xe2x80x9c0,xe2x80x9d and the state of high threshold voltage is defined as an erased state xe2x80x9c1.xe2x80x9d To program data, high voltage pulses need to be applied repeatedly to a memory cell until the threshold voltage of the memory cell becomes lower than a prescribed voltage (program verify voltage PV). In addition, to erase data, high voltage pulses need to be applied repeatedly to the memory cell until the threshold voltage of the memory cell becomes higher than a prescribed voltage (erase verify voltage EV). Thus, when programming and erasing data, a verify operation must be performed for determining whether the threshold voltage of the memory cell has reached the prescribed voltage or not. The verify operation is performed using a sense amplifier for performing a normal read (xe2x80x9creadxe2x80x9d for short) operation in a similar manner.
FIG. 10 is a circuit diagram representing an arrangement of a conventional sense amplifier. As shown in FIG. 10, a sense amplifier 1 includes a verifying P-channel MOS transistor 2, a normal-read P-channel MOS transistor 3, an inverter 202, an N-channel MOS transistor 203, an inverter 204, and a switch 207. Switch 207 selects transistor 2 during the verify operation and selects transistor 3 during the normal read operation. Inverter 202 compares a memory cell current Icell that flows through a non-volatile memory cell 10 with a sense amplifier load current I2 or a sense amplifier load current I3. As a result, sense amplifier 1 can determine the state of memory cell 10.
During the verify operation and the normal read operation, the voltage of a source line SL attains a ground voltage, and the voltage of a word line WL attains a power-supply voltage Vcc. Thus, memory cell current Icell flows to memory cell 10.
During the verify operation, transistor 2 supplies sense amplifier load current I2 which is m times a constant current I1. Constant current I1 is generated by a constant-current source 6. Constant-current source 6 includes an N-channel MOS transistor 7 and a P-channel MOS transistor 8. Transistor 7 has a constant reference voltage VREF applied at a gate so that it can supply constant current I1 that is independent of power-supply voltage Vcc. Transistor 2 and transistor 8 together form a current mirror circuit. The size of transistor 2 is m (mirror coefficient) times that of transistor 8. Thus, transistor 2 is capable of supplying sense amplifier load current 12 which is m times constant current I1.
On the other hand, during the normal read operation, transistor 3 supplies sense amplifier load current I3. Transistor 3 is independent from constant-current source 6, and has a ground voltage applied to a gate so that transistor 3 can supply sense amplifier load current I3 that is dependent on power-supply voltage Vcc.
FIG. 11 is a graph showing the relations of the voltage of the word line to the sense amplifier load current and the memory cell current.
During a program verify operation for verifying whether memory cell 10 has been programmed or not, a program verify voltage PV is applied to a word line WL, and program pulses are continually applied to memory cell 10 until a memory cell current Icell0 that is to flow through memory cell 10 when data is xe2x80x9c0xe2x80x9d becomes greater than sense amplifier load current I2.
On the other hand, during an erase verify operation for verifying whether memory cell 10 has been erased or not, an erase verify voltage EV is applied to word line VL, and erase pulses are continually applied to memory cell 10 until a memory cell current Icell1 that is to flow through memory cell 10 when data is xe2x80x9c1xe2x80x9d becomes smaller than sense amplifier load current I2.
From memory cell 10 in the programmed state (data xe2x80x9c0xe2x80x9d) or in the erased state (data xe2x80x9c1xe2x80x9d) thus formed, data xe2x80x9c0xe2x80x9d or data xe2x80x9c1xe2x80x9d is read using transistor 3 of sense amplifier 1.
A normal-read sense amplifier load current I3 depends on power-supply voltage Vcc, and becomes greater as power-supply voltage Vcc becomes higher as shown in FIG. 11. Power-supply voltage Vcc fluctuates between a Vcc upper limit and a Vcc lower limit shown in FIG. 11.
When memory cell 10 is in the programmed state, or when data xe2x80x9c0xe2x80x9d is stored in memory cell 10, memory cell current Icell0 is greater than normal-read sense amplifier load current 13. As a result, sense amplifier 1 outputs an H (logic high) level signal.
On the other hand, when memory cell 10 is in the erased state, or when data xe2x80x9c1xe2x80x9d is stored in memory cell 10, memory cell current Icell1 becomes smaller than normal-read sense amplifier load current I3. As a result, sense amplifier 1 outputs an L (logic low) level signal.
FIG. 11 shows a read margin xcex94Ia at the Vcc lower limit and a read margin xcex94Ib at the Vcc upper limit. The smaller the fluctuation range of power-supply voltage Vcc, the greater read margins xcex94Ia and xcex94Ib become, whereby a stable read operation becomes possible.
The conventional sense amplifier, however, has such problems as described below.
One problem is that read margin xcex94Ia at the Vcc lower limit becomes smaller as the temperature gets lower. FIG. 12 is a graph of a vicinity XII of the Vcc lower limit in FIG. 11 shown enlarged. In FIG. 12, memory cell currents Icell0 and normal-read sense amplifier load currents I3 at a low temperature LT, a room temperature RT, and a high temperature HT (LT less than RT less than HT) are respectively shown. As shown in FIG. 12, memory cell current Icell0 at the Vcc lower limit becomes smaller as the temperature gets lower. On the contrary, normal-read sense amplifier load current I3 at the Vcc lower limit becomes greater as the temperature gets lower. Thus, read margin xcex94Ia at the Vcc lower limit becomes smaller as the temperature gets lower. In FIG. 12, the read margin at room temperature is denoted by xcex94Ia@RT, the read margin at a high temperature is denoted by xcex94Ia@HT, and the read margin at a low temperature is denoted by xcex94Ia@LT.
Another problem is that read margin xcex94Ia at the Vcc lower limit varies according to the variation of the process. As shown in FIG. 10, N-channel MOS transistor 7 generates constant current I1 according to reference voltage VREF, and this current I1 becomes smaller as a threshold voltage Vthn of transistor 7 gets higher. Thus, the verifying sense amplifier load current I2 also becomes smaller as threshold voltage Vthn of transistor 7 gets higher. FIG. 13 is a graph of the vicinity XII of the Vcc lower limit in FIG. 11 shown enlarged. In FIG. 13, memory cell currents Icell0 and verifying sense amplifier load currents I2 at a low threshold voltage LVthn, a standard threshold voltage MVthn, and a high threshold voltage HVthn are respectively shown. At the Vcc lower limit, memory cell current Icell0 and verifying sense amplifier load current I2 become smaller as threshold voltage Vthn gets higher. Consequently, sense amplifier 1 might determine that the programming is completed even when memory cell current Icell0 is small during the verify operation. Thus, read margin xcex94Ia at the Vcc lower limit becomes smaller as threshold voltage Vthn of transistor 7 becomes higher. In FIG. 13, the read margin at a low threshold voltage is denoted by xcex94Ia@LVthn, the read margin at a standard threshold voltage is denoted by xcex94Ia@MVthn, and the read margin at a high threshold voltage is denoted by xcex94Ia@HVthn. Threshold voltage Vthn of transistor 7 varies according to process variation. As a result, read margin xcex94Ia at the Vcc lower limit varies according to the process variation.
The object of the present invention is to provide a non-volatile semiconductor memory device provided with a sense amplifier having a stable read margin that is independent of the temperature fluctuation and the process variation.
According to one aspect of the present invention, a non-volatile semiconductor memory device is provided with a non-volatile memory cell, a constant-current source, and a sense amplifier. The constant-current source generates a constant current. The sense amplifier detects the threshold voltage of the non-volatile memory cell. The sense amplifier includes a load current supplying circuit and a comparing circuit. The load current supplying circuit supplies a load current according to the constant current during a read operation and a verify operation. The comparing circuit compares a memory cell current that flows through the non-volatile memory cell with the load current.
In the above-described non-volatile semiconductor memory device, a sense amplifier is used for both the purposes of reading and verifying so that the characteristics of the sense amplifier and the characteristics of the non-volatile memory cell can be readily matched, while the layout area required for the sense amplifier can be reduced.
Preferably, the constant current has the positive temperature characteristic.
As a result, the load current also has the positive temperature characteristic. On the other hand, the memory cell current has the positive temperature characteristic at the lower limit of the power-supply voltage so that the read margin does not get smaller at low temperatures, and a stable read margin not dependent on the temperature can be ensured.
The constant-current source preferably is a bandgap reference circuit.
Thus, a constant current is generated according to a diffusion potential (also referred to as a built-in potential) of a PN junction. Therefore, a stable load current can be supplied even with process variations.
According to another aspect of the present invention, the non-volatile semiconductor memory device is provided with a non-volatile memory cell, a constant-current generating circuit for generating a constant current, and a sense amplifier. The sense amplifier includes a first load current supplying circuit, a second load current supplying circuit, a switch, and a comparing circuit. The first load current supplying circuit supplies a first load current that remains constant against the temperature fluctuation according to the constant current during the verify operation. The second load current supplying circuit supplies a second load current according to the constant current during the read operation. The switch selects the first load current during the verify operation, and selects the second load current during the read operation. The comparing circuit compares the memory cell current that flows through the non-volatile memory cell with the load current selected by the switch.
In the above-described non-volatile semiconductor memory device, the verifying load current remains constant against the temperature fluctuation so that an accurate verify operation can be performed.
Preferably, the constant-current generating circuit includes a first constant-current source and a second constant-current source. The first constant-current source generates a first constant current having the positive temperature characteristic. The second constant-current source generates a second constant current having the negative temperature characteristic. The first load current supplying circuit includes a first transistor and a second transistor. The first transistor supplies to a switch a first current proportional to the first constant current. The second transistor supplies to the switch a second current proportional to the second constant current along with the first current.
Thus, the first current has the positive temperature characteristic, while the second current has the negative temperature characteristic. Since the first and second currents are combined, the first load current has no temperature characteristic.
Preferably, the second load current supplying circuit includes a transistor for supplying to a switch a second load current proportional to the first constant current.
Thus, the second load current has the positive temperature characteristic. Consequently, a stable read margin independent of the temperatures can be ensured at the lower limit of the power-supply voltage.
More preferably, second load current supplying circuit further includes a resistor connected to a power supply and connected in parallel to a third transistor.
Thus, a current that is dependent on the power-supply voltage flows through the resistor. Consequently, the second load current has a power-supply voltage dependency as well as the temperature dependency so that the read margins at the upper limit and the lower limit of the power-supply voltage can be further increased.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.